Verilog HDL Through Examples

Learn Verilog HDL to model digital circuits from the scratch through various examples

Hey there, I welcome you all to my course ‘Verilog HDL through Examples’

What you’ll learn

  • Verilog HDL.
  • Digital Design in Verilog HDL.

Course Content

  • Introduction –> 2 lectures • 6min.
  • Understanding all the basic components of Verilog code –> 3 lectures • 23min.
  • Writing our first code in Verilog – Example 1 –> 4 lectures • 22min.
  • Dataflow Modelling and Behavioral Modelling for Example 1 –> 2 lectures • 16min.
  • Example 2 – Half adder design using all the three types of modelling –> 3 lectures • 14min.
  • Example 3 – Full adder design using all the three types of modelling –> 2 lectures • 21min.
  • Example 4 – 4 bit Parallel Adder design in Verilog –> 2 lectures • 21min.
  • Example 5 – Carry Look Ahead Adder in Verilog –> 3 lectures • 23min.
  • Example 6 – Code Converters in Verilog –> 2 lectures • 24min.
  • Example 7 – Multiplexers and Demultiplexers in Verilog –> 3 lectures • 31min.

Verilog HDL Through Examples


  • Yes, A basic knowledge in Digital Electronics.

Hey there, I welcome you all to my course ‘Verilog HDL through Examples’


Why Verilog?


1. To describe any digital system – microprocessor, memory, flip flop, Verilog is used. Hence it’s called as a hardware description language.


2. Using Verilog, we can model any electronic component and generate the schematic for the same.


3. For timing analysis and test analysis of circuits, Verilog is apt.


Highlights of the course:


1. Key differences between a programming language like C, C++ or Python and a hardware description language like Verilog, VHDL, SystemVerilog are clearly


2. All the fundamental concepts of Verilog are explained through standard combinational and sequential circuits.


3. Learning through examples make them very simpler to learn.


4. Proper theoretical explanation is provided for each of the circuit that is implemented in verilog in this course.


5. Testbench for each design and knowing how to test and validate them.


6. Creating Finite State Machines in Verilog.


7. Download the code and design for each of the circuits in the resources section.


8. Getting to know how to use EDA Playground for Verilog coding and how to generate the output waveform using EPWave.


9. Some of the key concepts of Verilog like

Levels of Abstraction, Two types of assignments, Producing delay, generating clock, Procedural assignments are all explained clearly.

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